1. Field of the Invention
This invention relates to a programing circuit for programming data into, for example, an EPROM (Erasable Programmable Read Only Memory), and more particularly to a programming circuit for use in a nonvolatile semiconductor memory device comprising a plurality of memory cells (hereinafter referred to as differential cells), each including a pair of cell transistors into which different data items are programmed in accordance with input data.
2. Description of the Related Art
When data is programmed an EPROM cell, for example, a high voltage is applied to the drain and control gate of the cell transistor included in the cell array, such that hot electrons flow from a channel region into the floating gate of the cell transistor, raising the threshold voltage of the cell transistor.
FIG. 5 shows a conventional programming circuit. A data input circuit 11 includes a NOR circuit 11a and an inverter circuit 11b which are connected in series. A write enable signal WE (holding the level "L" in a programming mode) and input data Din are supplied to the NOR circuit 11a. A program control circuit 12 is connected to the output terminal of the data input circuit 11. The program control circuit 12 includes a level shift inverter circuit 12a and a programming transistor 12b. The level shift inverter circuit 12a, whose input terminal is connected to the output terminal of the inverter circuit 11b, converts a 5 V signal into a 12.5 V signal, for example. The gate, drain, and source of the programming transistor 12b are respectively connected to the output terminal of the level shift inverter circuit 12a, a power supply V.sub.pp, and the drain of the cell transistor included in a memory cell (not shown).
The circuit shown in FIG. 6, for example, is employed as the level shift inverter circuit 12a.
In FIG. 6, an N-channel transistor N1 and a P-channel transistor P1 form an inverter circuit, the current path of the transistor N1 and that of the transistor P1 connected in series. The gate of the transistor N1 is connected to an input terminal IN, and the sources of the transistors N1 and P1 both are connected to an output terminal OUT. Transistors N2 and N3, whose current paths are connected in series between the input terminal IN and the gate of the transistor P1, are protection transistors which cut the current path between V.sub.cc and V.sub.PP. The gate of the transistor N2 is connected to a power supply V.sub.cc of e.g. 5 V. The gate of the transistor N3 and the source of the transistor P1 are coupled via a transistor N4 to a power supply V.sub.pp of e.g. 12.5 V. Transistors P2 and N5, which are connected to the gate of the transistor N3 and the sources of the transistors P1 and P3, form a leak circuit which keep the source level of transistors P1 and P3 stable. Further, a transistor P3 is connected between the source and gate of the transistor P1, and the gate of the transistor P3 is connected to the output terminal OUT. The transistor P3 is designed to feed back an output voltage to the gate of the transistor P1 so as to certainly turn the transistor P1 off when a signal having the level "1" is input from the input terminal IN.
When data is programmed into a cell transistor (not shown), the data input circuit 11 shown in FIG. 5 generates input data Din* on the basis of a write enable signal WE and the input data Din. The data Din* as generated is supplied to the transistor 12b through the level shift inverter circuit 12a such that the transistor 12b is turned on/off, thus allowing data to be programmed into the cell transistor.
When differential cells are used as memory cells, the program control circuit 13 shown in FIG. 7 is conventionally employed. The same circuit elements as those shown in FIG. 5 will be denoted by the same reference numerals in FIG. 7, and only the circuit elements which are not shown in FIG. 5 will be described in the following.
In the program control circuit 13 shown in FIG. 7, the input terminal of an inverter circuit 13a is connected to the output terminal of the data input circuit 11. The output terminal of the inverter circuit 13a is connected to one input terminal of a NAND circuit 13b, as well as to one input terminal of a NAND circuit 13d via an inverter circuit 13c. The input terminal of an inverter circuit 13e is connected to one input terminal of the NOR circuit 11a. The output terminal of the inverter circuit 13e is connected to the other input terminal of the NAND circuit 13b, and also to the other input terminal of the NAND circuit 13d. The write enable signal WE is supplied to the NAND circuits 13b and 13d through the inverter circuit 13e. The output terminal of the NAND circuit 13b is connected to the gate of a programming transistor 13h via a level shift inverter circuit 13f, while the output terminal of the NAND circuit 13d is connected to the gate of a writing transistor 13i via a level shift inverter circuit 13g. The configuration of each of the level shift inverter circuits 13f and 13g is as shown in FIG. 6.
In a programming mode, the program control circuit 13 programs different data into a pair of cell transistors in accordance with input data. In a non-programming mode, the program control circuit 13 prevents a high voltage from being applied to the drains of the cell transistors, by using the write enable signal WE.
In the programming mode, the write enable signal may hold the level "H", depending upon the circuit logic employed.
Incidentally, a pair of cell transistors included in a differential cell have the same low threshold voltage before data is programmed therein. That is, the cell transistors are both in the "1" state. When data is programmed into the differential cell, two different data are generated by the program control circuit 13 in accordance with the input data. The different data as generated are programmed into the cell transistors by a programming transistor.
In the conventional programming circuit shown in FIG. 7, the data input circuit 11 and the program control circuit 13 are simultaneously placed in an operation state by the write enable signal WE. In practice, however, after the program control circuit 13 has been placed in an operation state, there is a time until the data input circuit 11 outputs the data Din* (this will be hereinafter referred to as "until the input data Din* is established within the data input circuit 11"). If there is a relatively long time until the input data Din* is established, a pair of cell transistors may be erroneously programmed. The data is temporarily written into the erroneously selected cell transistor of paired cell transistors, as a result of which the threshold voltage of one of them increases. Thereafter, when the input data Din* is established, the cell transistor in which the data is to be programmed is selected and the data is programmed therein, with the result that the threshold voltage of one of them increases. The cell transistor, whose threshold voltage has increased, is in the "0" state.
Thus, when a cell transistor of a paired cell transistors is erroneously selected and data is programmed into the cell transistor selected, the threshold voltage of erroneously selected cell transistor increases and remains as is. The cell transistor whose threshold voltage has thus substantially increased is in the "0" state, while the other cell transistor is in the "1" state. In this case, the difference between the threshold voltages of the two cell transistors is smaller than that between the threshold voltages of another pair of cell transistors in which data has been programmed without a write error.
When data is read out from a differential cell, the difference between the threshold voltages of the cell transistors included in the differential cell is detected as the difference between the currents flowing through the cell transistors. A sense amplifier amplifies the current difference and outputs it as data. If, however, the difference between the threshold voltages of the cell transistors is small, the sense amplifier cannot detect it, resulting in a low read-out speed or incorrect data being output from the sense amplifier.